Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips

Brain network is a large-scale complex with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In article, we propose to synthesize brain-network-inspired interconnections for network-on-chips. First, method generate topologies limited scale-free power-law small-world have low total link length extremely average hop count approximately proportional the logarithm of size. addition, given applications, considering topologies, present an application mapping method, including task deterministic deadlock-free routing, minimize power consumption count. Finally, cycle-accurate simulator BookSim2 used validate architecture performance different synthetic traffic patterns test cases, real-world communication networks graph processing application. Experiments show that, compared other methods, network-on-chips (NoCs) generated by proposed significantly lower latency. Especially in applications tightly coupled inter-core communication, NoC has up 70% 75% latency than mesh-based NoCs.